(1) Field of the Invention
The present invention is directed to a semiconductor memory device having an error correction function and incorporating a redundancy configuration, thereby correcting both a soft error and a hard error.
(2) Description of the Related Art
A semiconductor memory device includes a large number of memory cells arranged along rows and columns which are orthogonal to each other. A density of defects generated in such a semiconductor memory device during manufacturing is relatively independent of the integration density of the device, but is dependent on semiconductor manufacturing technology. Therefore, the higher the integration density of the device, the greater the ratio of the number of normal memory cells to that of defective memory cells. This is one of the advantages obtained by increasing the integration density of a semiconductor memory device. Nevertheless, if the device includes even only one defective memory cell, which is called a hard error cell, the device cannot operate normally, and therefore, the device is scrapped.
To be able to operate a semiconductor memory device despite a hard error cell, a semiconductor memory device in which a redundancy memory cell array is incorporated with a main memory cell matrix along rows or columns thereof has been developed. In this device, when a hard error cell is detected, the redundancy memory cell array is used instead of a row memory cell array or a column memory cell array including the hard error cell. Accordingly, in a semiconductor memory device including such a redundancy memory cell array, the manufacturing yield thereof can be improved. Note that this redundancy technique can be applied only to previously determined hard errors. That is, once hard error cells are determined, other errors cannot be corrected after the determination of the hard error cells.
On the other hand, as the capacity of a semiconductor memory device is increased to 256 Kbits, 1 Mbits, and 4 Mbits, in order to reduce the size of the memory cells, the generation rate of soft errors due to .alpha.-rays has also increased. Such soft errors are corrected by an error checking and correcting (ECC) circuit, not by the above-mentioned redundancy technique. For this purpose, a dynamic random access memory (RAM) incorporating an ECC circuit of a two-dimensional virtual matrix type parity checking (or horizontal and vertical type parity checking) is known (see: T. Mano et al., "Circuit Techniques for a VISI Memory", IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5, pp. 463-469).
The above-mentioned redundancy technique can be combined with the improved ECC technique to enable the correction of not only the previously determined hard errors but also soft errors or hard errors caused after the determination of the previously determined hard errors. However, since the two-dimensional virtual matrix parity-checking has a predetermined logic for outputting data in response to a selected memory cell, it is impossible to simply replace a defective row or column with the redundancy row or column. Therefore, unless a great number of circuit elements for preventing the previously determined defective hard errors from entering the two-dimensional virtual matrix are used, it is difficult to combine the redundancy technique with the improved ECC technique.